IDT WinChip
Posts: 237
 
Location: USA | Multiprocessor support!
Lots of information and some answers. Looks like an email of a datasheet for the UMC U5S series.
http://datasheets.chipdb.org/UMC/U5S.txt
— SU.HARDW.PC.MOTHERBOARD (2:5020/299) —————————————— SU.HARDW.PC.MOTHERBOARD —
From : Sergey Kutikin 2:5020/324.16 Sun 19 Mar 95 03:55
Subj : UMS U5S è êýø
————————————————————————————————————————————————————————————————————————————————
ß ïîäóìàë,ìîæåò áûòü ýòî áóäåò èíòåpåñíî:
-------------------------------------------------------------------------
(C) UMC 1993,1995 U5S Introduction
-----------------
Compatible with Industry-Standard 486 SX System Management Mode
* 32-bit A/D buses and registers * GREEN CPU: fully static
* Dynamic 8/16/32-bit data-bus sizing design with SMM power
* Virtual,demand-paged memory managment management.
* On-chip 8 Kbyte,integrated,four-way * Accessible with interrupts.
associative instruction/data cache. * Automatic save/restore of
interrupted states.
Faster Execution * Transparent to operating
system.
* Executes frequently used instructions
30% to 48% faster than 486SX processor Binary Compatible with x86
at same clock rate. Software
* Burst data bus transfers: 80 MBytes/sec * Executes 486SX instructions.
at 25 MHz,106 MBytes/sec at 33 MHz, * Supports Windows,WindowsNT,
128 MBytes/sec at 40 MHz. MS-DOS,OS/2 and UNIX.
Standard 168-Pin PGA and 208-Pin LQFP Debug and Test Support
Package * Built-in self test.
* Hardware debug and test
0.6m(ïîäpàçóìåâàåòñÿ - "ìþ" CMOS Process registers.
5V or 3.3V Operating Voltage Multiprocessor Support
* Cache coherency.
* Support for level-2 cache.
* Multiprocessor instructions.
------------------------------------------------------------------------------
With my best regards,Sergey
--- GEcho 1.02+
* Origin: -= Breeze Ltd. =- (2:5020/324.16)
— SU.HARDW.PC.CPU (2:5020/299) —————————————————————————————— SU.HARDW.PC.CPU —
From : Vladimir Zhevnyak 2:5030/85.21 Sun 02 Jul 95 23:53
Subj : Re:U5S
————————————————————————————————————————————————————————————————————————————————
Äyìàþ, íàäî-áû ëþäÿì ïîìî÷ü, pàçüÿñíèòü ÷òî-ëè!
À òî ëåæèò ïîíèìàåøü ëè y ìåíÿ íà ñòîëèêå êíèæêà "U5S GREEN CPU"
1994-1995 DATA BOOK United Microelectronics Corporation.
Chapter 1: INTRODUCTION:
------------------------
The U5S GREEN CPU micriprocessors are a family of high-performance,
32-bit, static implementations of 486 SX architecture with energy-efficient
system management functions added. All processors ih the family support
the 486 SX instruction set at execution speed that, for most instructions,
are 30% to 48% faster than the 486 SX processor at same clock rate.
The ten processors ih the U5S family offer a mix of 25,33 or 40 MHz
operating speed for either the SX or DX sockets. The LV processors in the
family also support 3.3V operating voltage. All processors support a
power-saving System Management Mode. All processors are binary-compatible
with 486 SX operating system and application software, including software
that runs under Windows(R), WindowsNT(R), MS-DOS(R), OS/2(TM) and UNIX(TM).
The 8K byte on-chip cache and memory managenent logic implement fast,
coherent, demand-paged virtual memory management. The cache is software -
transparent so to be compatible with older x86 software.
All processors use a 1x external clock. The processors that operate at 5V
have a power consumption of 2.6W at 33MHz. Those that operate at 3.3V have
a power consumption of 1W at 33MHz. The static design supports clock freq-
uencies that can range dynamically down to zero to reduce power consumption.
The System Management Mode (SMM) in all processors is an added layer of
operating mode, above the standart Real, Protected, and Virtual-8086 modes.
SMM operates in an isolated memory space. It is transparent to all
operating-system and application software and support firmware-configured
function like intelligent, energy-efficiant power management functions.
The static design future, which allows clock frequencies to vary down
to zero, plus the optional SMM, support the design of energy-efficiant,
battery powered portable systems with extended battery life. The SMM is
implemented through a non-maskable System Management Interrupt (SMI)
which has higher priority than the NMI interrupt.
The improvements in the U5S instruction latencies relative to 486 XS
latencies, the compatibility of instruction execution and pinouts, and
the SMM for power management, make the U5S family of processors ideal for
supporting the broad base of existing x86 application and system software
on a wide range of system configurations, from desktop to portable.
Ôy, àæ âñïîòåë!
Çäåñü âñå íàïèñàíî è ñêàçàíî. Äyìàþ òåìy ïpî U5S ïîpà íàêpûâàòü !?
--- Îãîëåííûé Äåäyëÿ çèìîé 41 ãîäà.
* Origin: Cobra & Brosers Station (2:5030/85.21)
— SU.HARDW.PC.CPU (2:5020/299) —————————————————————————————— SU.HARDW.PC.CPU —
From : Aleksandr Konosevich 2:5004/9 Sat 06 Jan 96 18:27
Subj : CPU FAQ
* On-chip 8Kbyte, integrated, four-way associative instruction/data cache.
* 0.6m CMOS process
* 5V or 3.3V Operating Voltage
* Support Windows(r), WindowsNT(r), MS-DOS(r), OS/2(r) and UNIX(r)
* Built-in self test
U5 S D LV - SUPER33
^ ^ ^ ^ ^
| | | | | Performance VS. Speed :
| | | | \ Super25: Superior Performance at 25 MHz
| | | | Super33: Superior Performance at 33 MHz
| | | | Super40: Superior Performance at 40 MHz
| | | |
| | | \ Voltage Supply :
| | | : 5V Operating Voltage
| | | LV : 3.3V Operating Voltage
| | |
| | \ Pin-Out Configuration and Power Consumption :
| | : SX PGA Socket with SMM Power Management Pins Built-in
| | D : DX PGA Socket with SMM Power Management Pins Built-in
| | F : LQFP Pin-out with SMM Power Management Pins Built-in
| |
| \ Series Code :
| S : 486SX Function Compatible
|
\ Family code :
U5 : UMC Microprocessor, Green CPU
Part-specific pin table :
Pin # Part U5S Part U5SLV Part U5SD
G15 SMIRDY# SMIRDY# SMIRDY#
A13 SMI# SMI# SMI#
A15 NMI NMI N.C.
B15 N.C. N.C. NMI
R17 SMIADS# SMIADS# SMIADS#
------
Edited by waybacktech 2017-02-28 5:32 PM
|
UMC U5SD ... Not actually a DX class processor?
